Phase detection system for at least one digital phase-modulated wave

ABSTRACT

A phase detection system for at least one digital phasemodulated wave, in which two products of a phase-modulated digital signal and two reference carrier waves each having the same frequency as the phase-modulated digital signal and a phase difference 90* therebetween are at first produced, so that a converted value which is a function of a phase difference between the phase-modulated digital signal and one of the reference carrier waves is found by integrating respectively the two products or by passing the two products in respective low-pass filters. The phase detection of the phase-modulated wave is performed by comparing the converted value with a reference phase. Compensation means may be further provided to compensate phase error in the converted value.

United States Patent Nakagome et a1.

I 3,697,881 1 1 Oct. 10,1972

Inventors: Yukio Nakagome; Kazuo Kawai,

Assignee:

Filed:

both of Tokyo; Hidetaka Yanagidaira, Ohmiya; Sotokichi Shintani; Hisakichi Michishita, both of Tokyo, all of Japan Kokusai Denshin Denwa Kabushiki Kaisha, Tokyo-to, Japan July 9, 1970 Appl. No.: 53,527

Foreign Application Priority Data July 10, 1969 Japan ..44/54094 Sept. 12, 1969 Japan ..44/72462 U.S. Cl. ..329/104, 325/320, 328/109,

329/110 Int. Cl. ..H04l 27/22 Field of Search ..329/50, 104, 110; 328/109,

[56] References Cited UNITED STATES PATENTS 3,522,541 8/1970 Gooding ..325/324 3,590,386 6/1971 Tisi et a1. ..325/321 3,049,673 8/1962 Barry ..329/104 3,253,223 5/1966 Kettel ..329/50 X 3,391,344 7/1968 Goldberg ..328/134 Primary ExaminerAlfred L. Brody Attorney-Robert E. Burns and Emmanuel J. Lobato [5 7 ABSTRACT A phase detection system for at least one digital phase-modulated wave, in which two products of a phase-modulated digital signal and two reference carrier waves each having the same frequency as the phase-modulated digital signal and a phase difference 90 therebetween are at first produced, so that a converted value which is a function of a phase difference between the phase-modulated digital signal and one of the reference carrier waves is found by integrating respectively the two products or by passing the two products in respective low-pass filters. The phase detection of the phase-modulated wave is performed by comparing the converted value with a reference phase. Compensation means may be further provided A to compensate phase error in the converted value.

6 Claims, 13 Drawing Figures 4-1 5-1 6-1- 7 1 l l f 2 MODULATOR lNTEGRATOR SAMPLER CONVERTER 4;2 s-m 5;2 6-04 6?2 to [8 MODULATOR INTEGRATOR SAMPLER CONVERTER PHASE 5- SHlF-TER 3 MEMORY fa l0 REFERENCE CARRIER GEN 2 SUBTRACTER CODER WWVWWWVWW PATENTED U 101973 v 3,697,881 sum 1 or 1 Si(t) Si+1(t) Fig. 1

4-1 5-1 6-1 7 1 S I Y I f I 2 'MODULATOR INTEGRATOR SAMPLER CONVERTER 4 2 5-0-$ 5;2 s-mi 6E2 io I8 MODULATOR INTEGRATOR SAMPLER CONVERTER L g 9 PHASE 5-0 6- SHIFTER 3 MEMORY id 10 REFERENCE CARRIER GEN. 2 SUBTRACTER CODER PATENTED 3 697 881 sum 3 or 7 YES CONVERT THE CONTENTCmi'I'QOF COUNTER TO A cone P. 4 SEND OUT ADD "1" 9- THE CODE TO COUNTER CALCULATE n 9i+%'mi-1+Kfi-1 RESET COUNTER PATENTEI'JMI 1 9 2 3,697,881

SHEET 3 0F 7 9 YMEMORY 4 9 CALCULk B MEMORY T N CIRCUIT 19 15 REGISTER DELAY cmcuw I 1 r CATE 21 24 CIRCUIT I CALCULAT' CALCULAT- me me cmcuw CIRCUIT GATE DELAY -COUNTER CIRCUIT CIRCUIT K mT mi 23 Fig. 5;

CALCULAT- m6 CONVER cmcun TER GATE CIRCUIT PATENTEDHBI 10 1912 3,697,881

SHEET N UF '1 I IV V VI & I1O j SCANNING CALCULAT. i' CODER MEMORY me O SAMPLER v CIRCUH- w l r PHASE CONTROL SHlFTER CIRCU T Fig. 6A REFERENCE CARRIER H GENERATOR r W V W I] I J r 12 SCANNING READ-ONLY CODER MEMORY SAMPLER MEMORV In--" L1 CALCULAT- ING CIRCUIT CONTROL CIRCUIT PATENTEIJnm 10 I972 sum 5 or 7 PHASE SHIFTER I III-1 CODER REFERENCE CARRIER GENERATOR i? 1 SCANNING I2 f2 SAMPLER PHASE SHIFTER REFERENCE A CARRIER 11-2 MEMORY CALCUAT- ING CIRCUIT GENERATOR CONTROL CIRCUIT PHASE SHIFTER III-n REFERENCE CARRIER GENERATOR Fig.7

PATENTEDBBT w 191 3,697,881

SHEH 8 0F 7 B c E F s I f j PCM I I i CODE ACCUMU- CODE CODE CODER CONV. LATOR CONV. comm REFERENEE D CARRIE GENERATOR 8 T|ME 21 22 23 f f 3 SHIFT CONVERSION v 9 MODIFIER 20-22 REGISTER TABLE 24 PHASE DETECTION SYSTEM FOR AT LEAST ONE DIGITAL PHASE-MODULATED WAVE This invention relates to a phase detecting system for at least one digital phase-modulated wave modulated to quantum or discrete phase positions in accordance with information signal or signals to be transmitted.

As the phase detection system, there are a delayed detection system and a synchronous detection system in a broad classification. The delayed detection system is employed for detecting a differential phase modulated wave so that the phase position of a signal element is compared with the phase position of an immediately preceding signal element to detect a phase difference between two successive signal elements. Ac-

cordingly, a delay circuit having a delay time equal to the duration of the signal element is necessary in this system. Moreover, it is necessary that the delay time of the delay circuit is correctly maintained over a necessary frequency range. On the other hand, a reference carrier generator is necessary in the synchronous detection system to obtain a reference phase position. In this case, the phase position of the reference carrier is usually regulated by the use of phase-information transmitted from the sending side or by detecting phase-information from the received signal. In this case, transmission of the phase information is necessary by the use of another communication channel so that this is uneconomical and unusual. Moreover, it is very difficult to detect phase-information from the received signal and regulate the reference carrier generator.

An object of this invention is to provide a phase detection system of a digital phase-modulated wave or waves capable of performing phase detection corresponding to the delayed phase detection system or the synchronous detection system by a single circuit without complicated delay circuits and regulation circuits and suitable to reduce to practice by use of digital circuitry and to form time-divisional circuitry for a plurality of phase-modulated waves.

Another object of this invention is to provide a phase detection system of at least one digital phase-modulated wave capable of performing phase detection by digital operation without use of a reference carrier generator having a feed back loop coupled to the digital phase-modulated wave.

In accordance with a first feature of this invention, two products of a phase-modulated digital signal and respective two reference carrier waves each having the same frequency as the phase-modulated digital signal and a phase difference 1r/2 therebetween are at first produced, so that a value which is a function of a phase difference between the phase-modulated digital signal and one of the reference carrier waves is found by integrating respectively the two products or by passing the two products in respective lowepass filters, whereby phase detection of the phase-modulated digital signal is performed.

In accordance with a second feature of this invention, the phase of each signal element of the phasemodulated digital signal detected as mentioned above is temporarily stored as a stored phase, and this stored phase is replaced by a phase position of an immediately succeeding signal element similarly detected by the use of a phase difference between successive two signal elements.

vention has following merrits:

1. Since phase information is represented by digital information, phase information can be correctly represented by increasing the number of digits of the digital information.

2. Even if an oscillator is employed for generating reference carriers, it is not necessary that the frequency of the oscillator is regulated. Accordingly, the stability of the oscillation frequency of the oscillator is very high while feed back means is not necessary. These are suitable to low cost of the system.

3. A plurality of phase-modulated digital signals can be phase-detected in a time-divisional manner, so that the system can be formed in a small size and have a low cost.

The principle, construction, operation and merits of the system of this invention will be better understood from the following more detailed discussion in conjunction with the accompanying drawings, in which:

FIG. I is a wave form for describing an example of a digital phase-modulated wave applied to the system of this invention;

FIGS. 2 and 9 are vector diagrams explanatory of the principle of phase modulation in a phase-modulated wave applied to the system of this invention;

FIG. 3 is a block diagram for illustrating an embodiment of this invention;

FIG. 4 is a flow-chart explanatory of the operation of the system shown in FIG. 3;

FIG. 5 is a block diagram for illustrating a part of another embodiment of this invention;

FIGS. 6A, 6B, 7 and 8 are block diagrams each for illustrating another embodiment of this invention;

FIGS. 10 and 11 are block diagrams each for illustrating an example of a circuit used in the embodiment shown in FIG. 8; and

FIG. 12 shows characteristic curves explanatory of the operation of the example shown in FIG. I 1.

The principle of this invention will first be described. In this case, phase detection of an eight-phase differential phase-modulated wave transmitting three bits of information for each signal element is taken as an example, With reference to FIG. 1 showing a wave form of areceived signal, if the instantaneous level, phaseposition and amplitude of a signal element and the angle frequency of the carrier are assumed respectively as 5 (1), (b w and A, the instantaneous level of an i-th signal element S,(t) can be indicated as follows:

S,(r)=A cos(w t+,,) 1 In this case, the time t satisfies a condition '0 s t T if the duration of the signal element is indicated by T. Accordingly, the time t is zero at the start of the signal element and the value T at the termination of the signal element.

In this system, a reference carrier wave having the same frequency as the received signal is employed to of the general meaning, the product of the reference carrier wave and the received wave. can be indicated as follows:

+Al2.c c +(t+.)) (2) This product output is passed through a low pass filter so that a second member of the equation (2) is obtained. In this case, since the value W is substantially equal to the value w,, the output is substantially equal to a value A/2.cos (r b The second member of the equation '(2) can be also obtained by integrating the product output during a duration 1- equal to n/2-multiple of the period of the carrier wave. In other words, the duration 1' is equal to a value 21r/w n, where n is a positive integer. Namely, the integration of a first member is as follows:

Moreover, since a value (w, w,)t is substantially equal to zero in view of a condition w z w,, an integration of the second member is as follows:

I= cos (i-) In a similar manner, a product of the received signal and another reference signal having a phase position different by 11/2 from the reference carrier is as follows:

A cos( w (11,) cos (w,t d), 1r/2) A/2.cos((w w,)t d), d), 11/2) +A/2- c +(r.)+1r/2) The second member only of the equation (4) can be also obtained by passing the product output into a low pass filter. In this case, since a value w is substantially equal to a value w,, the output of the low-pass filter is as ollows:

On the other hand, if the product output is integrated during a duration 1', an integration of the first member of the equation (4) is as follows:

Moreover, an integration of the second member of the equation (4) is as follows:

A/2.cos((, 1r/2) =A/2.sin(..) This is an output of this integration.

If the signals indicated in the equations (3) and 5) are assumed as follows:

yi= A r/2- 0 (4n 4n) i (dh 1%) the following relationship is satisfied.

Therefore, a phase difference 1 between the received signal having a phase position do, and the reference carrier wave having a phase position can be indicated as follows:

dn du n/yi (8) This relationship is also obtained in a case of passing into the low-pass filter by the ratio of two outputs.

As mentioned above, the product of the reference carrier wave and the received signal and the product of another reference wave having a phase position different by 1r/2 from that of the reference carrier wave are at first obtained, and values x, and y, are obtained by integrating the products or passing the products into low-pass filters respectively. The phase difference (I between the received signal and the reference carrier wave is obtained by the use of the ratio x,/y,. However, since a function tan"(x,/y,) is not a univalent function, the value I is not uniquely determined for a value x,-/y,-. Therefore, if the following relationship is assumed by the use of an absolute value I xJy, of the value x,/y,, the value 4 can be indicated as shown in Table l in accordance with the positive or negative conditions of the values x, and y,.

TABLE I x, y, Quadrant Q,

+ first I '1 second 0, =1r I third 1h= 1: b fourth Ih= 2n 0 The value In can be obtained as mentioned above. Accordingly, when a valued of (i +1 )th signal element is similarly obtained, transmitted information can be detected by calculating a difference (1 1 in a ferences between adjacent two signal elements and Gray codes of the eight-phase phase-modulated wave are shown.

Three bits of information transmissible on each signal element having eight possible phases or phase positions are shown in a left most column. The phase difference d is represented with respect to an immediately preceding signal element as a reference. A multiplier multiplying a unit phase (11/4 in this case) corresponds to a transmitted code. The multipliers are shown at a right most column while codes corresponding to the multipliers are shown at the left most column.

With reference to FIG. 3, an example of this invention to perform the above-mentioned principle comprises an input terminal 1 for receiving an input phasemodulated signal, reference signal generator 2 for generating the reference carrier wave fa having a frequency substantially equal to the frequency of the input signal, a phase-shifter 3 having a phase shifting value 1r/2, modulation product circuits 4-1 and 4-2 (e.g.; ring-modulator), integrators 5-l and 5-2 each repeating integration operation every time 7 equal to an integer multiple of one half the period of the carrier of the input signal, samplers 6-l and 6-2 each sampling the output of the integrator 5-1 or 5-2 for each signal element at the termination of the integrating time 7, a converter 7 (eg, conversion table) for converting respective absolute values of the samplers 6-1 and 6-2 to the value b defined in the equation (9), a converter 8 (e.g.; conversion table) for converting respective outputs of the sampler 6-1 and 6-2 and the value 1 found at the converter 7 to the value I in accordance with Table l, a memory 9 storing respective values I and P of successive two signal elements, a subtracter 10 for obtaining a difference h 1 to codes in accordance with Table 2, and an output terminal 12 for the detected code.

In operation, the input signal is applied from the input terminal 1 to the modulators 4-1 and 4-2, so that a product of the received signal and the reference carrier wave f, is obtained at the output of the modulators 4- 1 while a product of the received signal and another reference carrier wave f having a phase position different by 11/2 from the phase position of the reference carrier wave f is obtained at the output of the modulator 4-2. These outputs of the modulators 4-1 and 4-2 are respectively defined by the equations (2) and (4) and applied respectively to the integrators 5-1 and 5-2 so as to be integrated for a time substantially equal to an integer multiple of one half the period of the carrier. These integration operations are performed for each signal element in synchronism with bit timing pulses applied from terminals 5-0. The bit timing pulses are usually transmitted from the sending side but may be independently generated at this receiving side. The values y, and x, defined by the equations (3) and (5) respectively are obtained from the integrators 5-l and 5-2 respectively. These outputs are sampled at the samplers 6-1 and 6-2 respectively and applied to the converters 7 and 8. The value 1 is obtained at the con ve'rter 7 from a ratio of the absolute value Ix, I to the absolute value y, I. The value 1 and the sampled outputs of the samplers 6-1 and 6-2 are converted to the value I at the converter 8. The output I of the conve'rter 8 is stored'in the memory 9, and the difference 1 Q is obtained from the substracter l0 and applied to the code 11. At the output terminal 12, a code corresponding to the difference (4 Q) is abtained.

In the above mentioned principle, a transmitted code is detected by the use of a difference between values D I which are found for successive two signal elements similarly to the delayed detection system. The above mentioned value 1 can be applied to perform synchronous detection as follows.

In this synchronous detection system, a phase regulation circuit for synchronizing the phase position of a reference carrier wave with the received signal is not employed. In the above-mentioned detection principle, the phase position I of an immediately preceding signal element is stored to find the difference between this phase position I and a phase position D of a succeeding signal element. In this detection system now mentioned, however, a code corresponding to a difference P 0, between a phase position P and a reference phase position 0, obtained in accordance with the received result of an immediately preceding signal element is found in accordance with the principle shown in Table 2. If following conditions are satisfied, namely:

where m is equal to a value 0, 1, 2, 3, 4, 5, 6 or 7, the value P is stored after changing to a value 0, in this case, it is conceivable that the stored phase position is synchronized with the received signal.

if a condition:

is satisfied, a phase difference is shown by a value (d, m .'rr/4).

If the value (d m,- ,.1r/4) is assumed a a value r a following condition is satisfied.

In this case, the phase position of signal element is indicated by a value mar/4 since an eight-phase phasemodulated wave is taken as an example. However, in a case of a N-phase phase-modulated wave, the phase position of signal element is indicated by a value mmr/ while a condition: 1r/N r, 1r/Nis satisfied. In this principle, a value 0 indicated by a following condition:

is stored to compensate an error of phase position. In this case, ll I shows a notation of mode 21:, so that if the value of a sum shown within the notation exceeds the value 21r thisvalue 21r is substracted from the sum to obtain the value 0, A difference P 0, is found for the receiving of each signal element by the use of the phase position 1 of the signal element and a phase position 0, stored as mentioned above. Moreover, a code corresponding to the signal element is obtained from a multiplier m of a unit phase corresponding to a phase difference d in accordance with the principle shown in Table 2.

The above principle will be further described in details with reference to a flow chart shown in FIG. 4. It is assumed that a transmitted code is detected from an i-th signal element and a compensated phase position 0, is stored in the memory. When an (i l)-th signal element is received, the phase position thereof is found as mentioned above. In this case, a difference P 0, is at first calculated as shown in the flow chart of FIG. 4. If the difference D 0,- is less than zero, a sum D Zr -0, is found and applied to a register R. However, if the difference D 0, is stored in the register R. If the contents r of the register R do not satisfy a condition: 1r/8 r 1r/8, a difference r /4 is found and l" is added to a counter. Thereafter, the condition: rr/8 r 1r8 is again tested. If the condition: 1r/8 r 1r/8 is satisfied, the contents m of the counter at this instant are coded to a code in accordance with the principle shown in Table 2 so that the code is sent out to, the output. Moreover, a sum I 0, Ir/4m Km l is found from the contents r of the register at this instant and stored, as a stored phase in the memory. In this case, a value K is a coefficient which meets with a condition: 0 K 1.

In the above explanation, it is assumed that a stored phase is already stored. However, it is not known what value is stored in the memory when a first signal element is received. The stored value is compensated for receiving of each signal element by repeating the above-mentioned operations, so that the stored value is corrected to a correct value. The speed of this correction is determined in accordance with the value of the coefficient K. If the coefficient K is equal to l as ,an extreme case, this phase detection corresponds to the delayed phase direction in which phase detection of a signal element is performed with respect to the phase 7 position of an immediately preceding signal element as a reference. On the other hand, if the coefficient K is equal to zero, a value 0 given at first is completely synchronized with the received signal so that this synchronized condition is thereafter maintained.

With reference to FIG. 5, an example of a circuit performing the above-mentioned synchronous phase detection will be described. In this example, a memory 9 is the same as the memory 9 shown in FIG. 3 and stores the phase position of a received signal element. A memory 14 stores the above mentioned stored phase 0,. A calculating circuit 13 (e.g.; conversion table) produces a difference D 0, by the use of the value 1 applied from the memory 9 and the stored phase 0, applied from the memory 14. If a condition: 0, 0is not satisfied, the difference I 0, is stored in a register 15. However, if a condition: 1 m 0 0 is satisfied, a value in 211 0, is stored in the register 15. A calculating circuit 24 tests whether or not the contents r of the register 15 meet with a condition: 1r/8 r 1r/8 in a case of detection of a eight-phase phase-modulated wave. If the contents r are not included within the above range, the contents r are applied through a gate circuit 16 to a calculating circuit 21. This calculating circuit 21 produces a difference r 1r/4 which is again stored in the register 15 through a delay circuit 19 having a very small delay time.

Moreover, the pulse from the calculating circuit 24 is applied to a counter 22. The contents r newly stored in the register 15 are tested by the calculating circuit 24. The above-mentioned condition: 1r/8 r 1r/8 is not satisfied, the above mentioned operations are repeated. When the condition: 1rl8 r 1rl8 is satisfied, the contents r of the register 15 passes through a gate circuit 17 opened in response to the pulse from the calculating circuit 24 and is applied to a calculating circuit 25. On the other hand, the contents m, of the counter 22 are converted to a code in a converter 23 in accordance with the principle shown in Table 2 to send out the code to an output terminal 26 through a gate circuit 18. The counting state of the counter 22 is reset at once in response to the output pulse of the calculating circuit 24 applied through a delay circuit 20. The calculating circuit 25 produces'a sum 1r/2.m, K.r by the use of the contents r of the register 15 and the contents m, of the counter 22 so as to be stored in the memory 14 and a new stored phase 0,.

An example of obtaining the timing pulses for controlling the integration period of the integrators (5-1 5- 2) will now be described. In a case where a modulation product of the received signal and the output of the reference carrier wave is performed at the modulator (4-1,4-2) as mentioned above, the output of the modulator can be divided into two parts one of which has a frequency substantially equal to the frequency of the reference carrier wave and the other of which is a lowfrequency signal having an instantaneous level changed in accordance with only digital information transmitted. If this low-frequency signal is separated from the former component by a low-pass filter, the timing pulses can be obtained so as to synchronize with characteristic instants of the low-frequency signal since the level of the low-frequency signal varies in accordance with digital information transmitted. Moreover, since the output of the low-pass filter (i.e.; the low-frequency signal) is proportional to values x, and y,, this output of the low-pass filter can be used in the place of the values x, and y A separated channel may be employed to transmit bit timing information for integration and sampling. Moreover, it is desirable that the integrating time for integrating the output of the modulator (4-1, 4-2) for each signal element is substantially equal to an integer multiple of one half the period of the carrier as mentioned above. However, if the period of the carrier is sufficiently smaller (e.g.; less than one several-th) than the duration of the signal element, integration error will be small even if the integration time is determined irrespective of the period of the carrier. Accordingly, the integration time may be determined so as to be equal to or smaller than the durationof the signal element irrespective of the period of the carrier. Furthermore,

the values of phase are represented in radians. However, values of phase represented in degrees can be also handled in this system.

In the above explanation, it is assumed that a phasemodulated wave is applied to the system of this invention. However, if a plurality of phase-modulated waves are applied to this system, common circuitry provided after the samplers (6-1, 6-2) can be used time-divisionaly for the phase-modulated waves. Moreover, if

the input signal is at first sampled and coded to a binary signal, all the circuits can be formed by digital circuits. If a high speed calculating circuit can be employed, the above mentioned modulation product and integration can be performed by a common calculating circuit.

With reference to FIG. 6A, an example, of this invention for receiving a plurality of phase-modulated waves having the same frequency comprises a reference carrier generator II which is the same as the reference carrier generator 2, a phase shifter III which is the same as the phase shifter 3, a scanning sampler I for scanning input signals applied from input terminals I,, I I,,, reference carriers obtained from the reference carrier generator II and the phase shifter III by the use of sampling pulses applied from a control circuit VII, a coder IV for coding the sampled output of the scanning sampler I, a memory V for temporarily storing the coded output of the coder IV, a calculating circuit VI for performing the above mentioned calculation for the contents of the memory V, and the control circuit VII for applying timing information to the circuits I, IV, V and VI.

If a read-only memory VIII is provided for semipermanently storing respective sampled values of the reference carriers after coded as shown in FIG. 6B, the reference carrier generator II and the phase shifter III can be eliminated. In this case, contents of the readonly memory VII is repeatedly read-out without sampling and coded for each sampling period as shown in FIG. 6A. Moreover, since two reference carriers have only a phase difference between each other, a common memory table can be used in a normal address condition and a condition where addresses are shifted from the normal address condition. In this case, however, a clock is necessarily provided in the control circuit VII so as to synchronize with the cycle of the reference carrier wave.

The above-mentioned explanation relates to detection operation of an eight-phase phase-modulated wave. However, the system of this invention can be applied to detect at least one phase-modulated wave having 2" possible quantum phase positions for transmitting n bit or bits of digital information on each signal element.

In the above explanation, it is assumed that the modulation product circuit (4-1, 4-2) produces an output signal having positive and negative possible polarities. However, if the modulation product circuit (4-1, 4-2) produces an output signal of single polarity, two circuits are necessary for the modulation product circuit (4-1 or 4-2).

With reference to FIG. 7, an example of this system for commonly phase-detecting a plurality of phasemodulated waves is provided with a plurality of reference carrier generators "-1, "-2, II-n for generating reference carrier waves respectively having the same frequency as frequencies f,, f f, of the phase-modulated waves, and a plurality of phase shifters III-1, III-2, III-n.

With reference to FIG. 8, another example of this invention will now be described. This example comprises, an input terminal A, a PGM coder B, a code converter C, a reference carrier generator D, an accumulator E, a code converter F, a code converter G for detecting transmitted phase information, and an output terminal II.

It is assumed that a plurality of eight-phase differential phase-modulated waves bit-synchronized with each other and allocated in frequency spaces l/T I-lerz are applied to the input terminal A. In this case, the time T is equal to or slightly less than the duration of each signal element of the phase-modulated wave. Eight quantum phases and codes to be transmitted on one of the eight-phase differential phase-modulated waves are shown in FIG. 9. Vectors shown in FIG. 2 indicate phase-shift from a reference phase (i.e.; phase position of vector MMM) in response to combination of mark (M) and space (S) of three channels or bits I, II and III. The above mentioned eight-phase differential phase-modulated waves are applied to the PCM coder B, which samples the applied signal by sampling pulses of several tens kilo-Herz and codes PCM codes of 10 bits by way of example. These PCM codes are codeconverted at the code converter C by the use of two reference carrier waves having a phase difference 1r/2 therebetween supplied from the reference carrier generator D. This code conversion corresponds to phase detection in an analogue system. The outputs of the code converter C obtained for the two reference carrier waves respectively are applied to the accumulator E, which accumulates separately the two outputs of the code converter C during each signal element and ends out respective accumulated results at the termination of each signal element to the code converter F. This operation corresponds to integration operation of an anlogue system. If it is assumed that respective phase differences between one of the reference carrier waves and the input signal and between the other of the reference carrier waves and the input signal are values I and I respectively, the two output codes of the accumulator E correspond respectively voltages proportional to cos D, and sin 1 respectively. Accordingly, the two output codes of the accumulator E can be converted to a code representative of the value I in the code converter F as mentioned below. The output of the code converter F is applied to the code converter G, which detects transmitted digital information in view of the principle of differential phase-modulation as mentioned below.

Respective parts of the example shown in FIG. 1 will be further described in details below. The PCM coder can adopt any type of PCM code. However, it is assumed in this case that the output code of the PCM coder B is a folded binary code. Moreover, it is assumed that the folded binary code is derived therefrom as a parallel configuration. However, if successive logical circuitry is designed so as to perform high speed operation, the output code of the PCM coder B may be derived therefrom in serial configuration.

The reference carrier generator D generates, for each phase-modulated wave, two reference carrier waves of rectangular wave form which have the same frequency substantially equal to the frequency of the phase-modulated wave and a phase-difference 90 from each other.

The code converter C converts the output of the PCM coder B in response to respective polarities l and of the two reference carrier waves from the reference carrier generator D. In this case, it is assumed for simple explanation that the number of the phasemodulated wave is one and the number of the reference carrier wave is also one. The most significant digit (MSD) of the PCM code is compared with the polarity of the reference carrier wave, so that the MSD is modified to l and 0 in response to the same polarity and different polarities of the above compared digit and wave. The PCM codes in which only the MSD is modified as mentioned above are applied to the accumulator E.

The accumulator E accumulates the converted PCM codes during the duration of each signal element and sends out the accumulated results at the termination of each signal element.

As mentioned above, respective phase detectio between one of the two reference carrier waves and the input phase-modulated wave and between the other of the two reference carrier waves and the input phasemodulated wave as well as integration of the respective results of the phase detections are digitally performed. The above phase detections are time-divisionally performed for the two reference waves by supplying alternately the two reference carrier waves from the reference carrier generator D to the code converter C. Moreover, two stages of registers are provided at the accumulator E to as to be connected in cascade with the accumulator E while the output of the two stages of registers are fed back to the accumulator E, so that contents of a preceding one of the two stages of registers are shifted to a successive one of the two stages of the registers in synchronism with the switching of the two reference carrier waves.

To handle a plurality of phase-modulated waves, a plurality of pairs of reference carrier waves are generated from the reference carrier generator D, and a plurality of combinations (two stages) of registers are provided in the accumulator E similarly as mentioned above, so that the registers are switched in synchronism with the switching of the carrier waves.

If two signals applied from the accumulator E to the code converter F are assumed as x and y, these signals x and y can be indicated as A.sin i and A.cos D This code converter F converts the values A.sin Q, and A.cos (D, to a value 1 indicated as a coded digital signal. in this case, this conversion may be performed by the use of a conversion table of tan z/y after obtaining a quotient x/y. However, division is unsuitable to high speed logical operation. Moreover, since the conversion table is designed for all combinations of values x and y, the device will become a very large size in accordance with the increase of the number of bits of the valuesx and y.

To eliminate the above defect, inhibited combinations of values it and y may be removed from the conversion table. In this case, since the required value I is equal to a value tanbc/y, the value I is not varied even if the respective values x and y are multiplied by the same multiplier. Accordingly, if respective MSD of the values x and y are both 0, the values x and y are both multiplied by a multiplier 2 (where N" is an integer) to shift by N bits so that the MSD of either the value x or y becomes always 1". Thereafter, combinations in each of which MSD of both the values x and y assume 0 are eliminated to increase preciseness. In Table 3, examples of inhibited combinations in a case where values it and y are each indicated by three bits of binary information are shown by mark TABLE 3 Inhibited Inhibited comb nations x y combinations x y 000 000 l 00 000 000 00 l l 00 00 l 000 0 l 0 l 00 0 l 0 000 0 l l l 00 O l l 000 l 00 l 00 l 00 000 l 0 l l 00 l 0 l 000 l l 0 l 00 l l 0 000 l l l l 00 l l l 00 l 000 l 0 l 000 00 l 00 1 l 0 l 00 l 00 l 0 l 0 l 0 l 0 l 0 00 1 0 l l l 0 l 0 l l 00 l l 00 l 0 l l 00 00 l 1 0 l l 0 l l 0 l 00 l l l 0 l 0 l I l 0 00 l 1 l l l 0 l l l l 0 l 0 000 l l 5 000 O l 0 00 1 l l 0 00 l 0 l 0 0 l 0 l l 0 0 l 0 010 01 l 1 10 0l 1 010 l 10 100 010 101 1 10 101 010 1 l0 1 10 l l 0 1 l0 1 l l l l l 0 l l 090 l l l 000 s 0 l l 001 l l l 001 s 011910 lll 010 0 l l 01 1 l l l 0] l a O l l 100 l l l 100 01 l 101 1 l l .101 0] l l 10 l l l l l 0 01 1 1 l 1 l l l l l I An example of the code converter F to perform the above-mentioned operation shown in FIG. 10 comprises a shift register 21 shifting signals x and y applied from terminals 20-1 and 20-2 respectively, a conversion table 22 formed by a semipermanent memory by way of example, and a modifier 23 modifying the output of the conversion table 22 by the use of the shifted information from the shift register 21.

As mentioned above, the output of the code converter F for one of the phase-modulated waves becomes codes each indicative of a phase difference between the input phase-modulated wave and either one of the two reference carrier waves. If it is assumed that each of the output codes of the code converter F is formed by eight bits of binary information, one complete phase cycle 360 can be represented by 256 steps. Accordingly, each of the quantum phase positions is precisely indicated by the use of a minimum value 360l256 14). In a case where the input phase-modulated wave has eight quantum phase positions, the contents of the eight bits of binary information vary for each signal element by a value equal to an integer multiple of a unit quantum phase 45 except the combination of polarities MMM of three channels as shown in FIG. 9. Moreover, a phase difference between adjacent two signal elements effectively varies in accordance with a frequency difference between the input phase-modulated wave and the two reference carrier waves. Accordingly, this phase difference (I can be indicated as follows in a case of eight quantum phases.

where K: an integer 0. l, 2, 3, 4, 5, 6 or 7 determined in accordance with the principle shown in FIG. 9;

6,: a phase difference between the phase-modulated wave and the two reference carrier waves; and an integer determined so as to make a value (0,- n.7r/4) less than the unit phase 'rr/4. Accordingly, the phase difference 6, can be indicated by the use of a value less than the unit phase 11/4. Since an angle less than the unit phase 11/4 can be indicated by lower value five bits in a pure binary code, the drift of the phase can be detected from the lower value five bits while a shift value between any two of the eight quantum phase positions and equal to an integer multiple of the unit phase 1r/4 can be indicated by the upper value three bits.

With reference to FIG. 11, an example of the code converter G will be described. In FIG. 11, a signal e, shows that this signal e consists of five digits from a fourth digit to an eight digit by way of example. The input of this code converter G applied from the code converter F is shown as a signal a, and applied to a cascade arrangement of a subtracter S,, a code converter C, and an accumulator I,. This cascade arrangement is smoothing means for compensating the above mentioned phase fluctuation less than the unit phase 1r/4. The accumulator I, performs an integration operation as mentioned above, and digits b, from output digits b, of this accumulator I, are fed back to the subtracter S,, in which the digits b, are subtracted from the digits a, Digits bf and digits b, are neglected without feedback to the subtracter 8,. However, the digits b, are shifted by three digits to higher digits so that the feed back value is multiplied by one-eighth. As the subtraction of the digits bf from the digits a, at the subtracter 8,, an error 0, from a desired value of compensation is obtained from the subtracter S, as a positive value since the digits 0, show only positive values. However, if negative digits are desirable to raise the convergent speed of the compensated output b,, the digits 0, are converted to negative digits at the code converter C,. If it is assumed that the digits 0, are indicated by a pure binary code and the error shown by the digits 0, increases, the digits c, vary from a state 0 0 0 0 to a state 1 l l l l and then restores to the state 0 O O 0 0. In this case, the convergent speed of the output digits b, becomes higher in a case where a range from a state 0 0 0 0 0 to a state 0 l l l l is positive while a range from a state I O 0 0 0 to a state I l l l is negative. Accordingly, if the digits c, are included in the range from the state 0 O 0 0 O to the state 0 l l l l, the digits c, are applied to the accumulator 1, without code-conversion in the code-conversion in the code converter C,. In this case, the accumulator l, successively adds the error signals (0, until convergence. However, if the digits 0, exceed the state 1 0 0 0 0, the digits c, are converted to a code which corresponds to a sum of the digits c, and a number 201 6indicated by a decimal representation. In other words, while the digits c, more than the states I 0 0 0 0 correspond to numbers sixteen to thirty-one indicated by a decimal representation, the digits c, are converted to any of numbers minus 16 to minus I. To perform this operation, since the accumulator I, is designed so as to have eleven bits of code configuration, complements for the full range (i.e.; 2048 of decimal representation) of the 11 bits of information' are produced in the code converter C, if the error is negative. The l 1 bits of code configuration at the accumulator 1, consists of eight bits covering 2w radians and three bits for shifting by three bits as feed back. Accordingly, if the error is a number 31, this error is converted at the code converter C, to a number 31 2016 2047. In this case, 1" is subtracted from the contents of the accumulator I,. As mentioned above, the contents of the accumulator l, is accumulated in the positive direction until a value 15 of the error and in the negative direction until a value 16 of the error. Accordingly, phase error included in the output of the code converter F is effectively compensated in the compensation means comprising the circuits 8,, C, and 1.

Since the reference carrier generator D is provided independently against the input phase-modulated wave, the reference carrier wave and the input phasemodulated wave have usually a frequency difference df. In this case, the above mentioned phase difference I drifts in a speed 21r.df.t. If the phase difference I increases as mentioned above, the above mentioned compensation means cannot compensate the error since the compensation operation of the compensation means is delayed as shown in FIG. 12. If the drift is negligible in comparison with the unit phase 7T/4, it is not necessary to compensate this drift. However, if the frequencies of the reference carrier wave and the input phase-modulated wave are incorrect, the drift must be compensated. A cascade arrangement comprising a subtractor 8,, a code converter 0,, an accumulator I and a code converter C is means for compensating this drift. The subtractor 8,, the code converter C and the accumulator I, forms compensating means similar to the cascade arrangement of the circuits 8,, C, and I mentioned above to compensate a drift component in the digits 0, In this case, however, the code converter C2 produces complements for a range 256 different from the range of the code converter C,. In other words, since the output e, of the accumulator I is formed by eight bits and the full range of this eight bits corresponds to the number 256, the output gf of the subtracter S becomes a number 3] 224 255 in a case where the output As mentioned above, the digits b, obtained after normal compensation operation by the circuits 8,, C, and I, and the digits h, obtained after drift-compensation operation by the circuits 8,, C 1, and C are added to each other at the adder A,, so that phase-drift and phase-error caused by the reference carrier wave generated independently to the input phase-modulated wave can be detected completely without no delay by the use of compensation technique mentioned above. It is very difficult to perform digitally in a high precise manner this detection operation of phase-error by an automatic phase control circuit having a feed back loop if the number of digit is small.

The above-mentioned correcting digits i obtained from the adder A correctly indicates phase error. Accordingly, the phase error and phase drift included in the digits a is eliminated by subtracting the correcting digits i, from the input digits a, at a subtracter S However, noise included in the input phase-modulated wave causes slight jitter at each quantum phase position. Since the digits j and the polarity combinations of three bits included in a signal element of the phase-modulated wave are shown in Table 4, the jitter caused by the noise is eliminated by adding digits R to the digits j at an adder A so as to perform addition of a value 'rr/ 8 and to produce digits shown in Table 4.

TABLE 4 Polarity 11.121; 1. 3 1

combinations 0 0 M M M 0 O 0 l 0 0 O l O O l O 0 0 l 0 M M S 0 'O l l 0 0 l l 0 l 0 0 0 l 0 0 M S S 0 l 0 l 0 l O l 0 l l O 0 i l l 0 M S M 0 l l l 0 I l l l O O O l O O O S S M l 0 0 l l O 0 l l O l O I 0 l 0 S S S l O l l l O l l l l O O l l O 0 S M S l l O l l I O l l l l O l l l 0 I S M M l l l l l l l l 0 0 0 0 A delay circuit DEL is provided so that output digits m indicate an immediately preceding signal element. Accordingly, when the digit m is subtracted from digits 1 at a subtracter S differential phase modulation component is eliminated, so that digits n represent a fixed-reference phase-modulated signal.

Since the digits n are pure binary codes while tee phase-modulation of the input differential-phase modulated wave is performed by Gray code, the digits n are converted to Gray code to obtain an correct output.

If a plurality of phase-modulated waves are applied to the input terminal A, the accumulators l, and I and the delay circuit DEL must be added more circuits in proportion to the increase of the number of the phasemodulated waves in the codeconverter G.

The above mentioned example mentioned with reference to FIGS. 8, l0 and 11 can be also applied to demodulate a phase-modulated wave or waves having 2" quantum phase positions for transmitting n-bits of binary information by each signal element as well as the phase-modulated wave of eight-quantum 'phase. Moreover, if a fixed-reference phase modulated wave or waves is/are to be demodulated, the delay circuit DEL and the subtracter 5, may be eliminated so that the output of the adder A is directly applied to the code converter C,.

What we claim is:

l. A phase detection system for at least one digital phase-modulated wave, comprising:

an input terminal for receiving a digital phase-modulated wave; a reference phase generator having means for generating a first reference carrier and a second reference carrier each having a frequency substantially equal to the frequency of said digi al phasemodulated wave and having a phase difference therebetween;

modulation product meanscoupled to the input terminal and the reference phase generator to produce a first modulation product of the first reference carrier and the digital phase-modulated wave and to produce a second modulation product of the second reference carrier and the digital phase-modulated wave;

conversion means coupled to the modulated product means to convert the first modulation product and the second modulation product to a converted signal indicative of a value corresponding to a phase difference between the digital phase-modulated wave and one of said first and second reference carriers; and

comparison means coupled to the conversion means to compare the converted signal with one of a plurality of possible discrete phase positions of the digital phase modulated wave so as to perform phase-detection of the digital phase-modulated wave.

2. A phase detection system according to claim 1, in which the conversion means comprises a pair of integrators each performing integration for each signal element of the digital phase-modulated wave.

3. A phase detection system according to claim 1, in which the conversion means comprises a pair of low pass filters.

4. A phase detection system according to claim 1, in which the system further comprises compensation means coupled to the comparison means to subtract a phase corresponding to a transmitted code and the reference phase from the phase position of the phasemodulated wave to obtain a phase error and having means to perform the phase compensation of the reference phase by the use of the phase error.

5. A phase detection system according to claim 1, in which the system further comprises a PCM coder arranged between the input terminal means and the modulation product means.

6. A phase detection system according to claim 5, in which the comparison means comprises phase-error detection means for detecting phase-error from lower digit values of the converted signal, a subtractor coupled to the conversion means and the phase-error detection means for subtracting the phase-error from all digit values of the converted signal, and demodulation means coupled to the subtractor for performing demodulation of the phase modulated wave by the use of higher bits only of the output digital values of the subtractor. 

1. A phase detection system for at least one digital phasemodulated wave, comprising: an input terminal for receiving a digital phase-modulated wave; a reference phase generator having means for generating a first reference carrier and a second reference carrier each having a frequency substantially equal to the frequency of said digital phase-modulated wave and having a phase difference 90* therebetween; modulation product means coupled to the input terminal and the reference phase generator to produce a first modulation product of the first reference carrier and the digital phase-modulated wave and to produce a second modulation product of the second reference carrier and the digital phase-modulated wave; conversion means coupled to the modulated product means to convert the first modulation product and the second modulation product to a converted signal indicative of a value corresponding to a phase difference between the digital phasemodulated wave and one of said first and second reference carriers; and comparison means coupled to the conversion means to compare the converted signal with one of a plurality of possible discrete phase positions of the digital phase modulated wave so as to perform phase-detection of the digital phase-modulated wave.
 2. A phase detection system according to claim 1, in which the conversion means comprises a pair of integrators each performing integration for each signal element of the digital phase-modulated wave.
 3. A phase detection system according to claim 1, in which the conversion means comprises a pair of low pass filters.
 4. A phase detection system according to claim 1, in which the system further comprises compensation means coupled to the comparison means to subtract a phase corresponding to a transmitted code and the reference phase from the phase position of the phase-modulated wave to obtain a phase error and having means to perform the phase compensation of the reference phase by the use of the phase error.
 5. A phase detection system according to claim 1, in which the System further comprises a PCM coder arranged between the input terminal means and the modulation product means.
 6. A phase detection system according to claim 5, in which the comparison means comprises phase-error detection means for detecting phase-error from lower digit values of the converted signal, a subtractor coupled to the conversion means and the phase-error detection means for subtracting the phase-error from all digit values of the converted signal, and demodulation means coupled to the subtractor for performing demodulation of the phase modulated wave by the use of higher bits only of the output digital values of the subtractor. 